View 8XC196KB_3343948.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. february 1995 copyright ? intel corporation, 1995 order number: 270679-005 8XC196KB advanced 16-bit chmos microcontroller romless or rom automotive y b 40 cto a 125 c ambient y 232 bytes of on-chip register ram y 8 kbytes of on-chip rom (optional) y high-performance chmos process y register-to-register architecture y 10-bit a/d converter with s/h y five 8-bit i/o ports y 28 interrupt sources y pulse width modulated output y powerdown and idle modes y high speed i/o subsystem y dynamically configurable 8/16-bit buswidth y full duplex serial port y dedicated baud rate generator y 1.725 m s 16 x 16 multiply y 3 m s 32/16 divide y 16-bit watchdog timer y 16-bit timer y 16-bit up/down counter w/capture y four 16-bit software timers y hold/holda bus protocol the 8XC196KB 16-bit microcontroller comes with 8 kbytes of on-chip mask programmable rom or in rom- less versions. all devices are high performance members of the 8096 microcontroller family. the 8XC196KB is pin-to-pin compatible and uses a true superset of the 8096 instructions. intel's chmos process provides a high performance processor along with low power consumption. to further reduce power requirements, the processor can be placed into idle or powerdown mode. bit, byte, word and some 32-bit operations are available on the 8XC196KB. with a 16 mhz oscillator, a 16-bit addition takes 0.495 m s, and the instruction times average 0.375 m s to 1.125 m s in typical applications. four high-speed capture inputs are provided to record times when events occur. 4 a 2 high-speed outputs are available for pulse or waveform generation. the high-speed output can also generate four software timers or start an a/d conversion. events can be based on the 16-bit timer or a 16-bit up/down counter. also provided on-chip are an 8 channel, 10-bit a/d converter with sample and hold, a serial port with synchronous/asynchronous modes and on-chip baud rate generator, a 16-bit watchdog timer, pulse width modulated output with prescaler and an on-chip clock failure detect circuitry. 270679 1 figure 1. 8XC196KB block diagram
automotive 8XC196KB 270679 3 figure 2. the 8XC196KB family nomenclature architecture the 8XC196KB is a member of the 8096 family, as such has the same architecture and uses the same instruction set as the 8096. many new features have been added on the 8cx196kb including: cpu features divide by 2 instead of divide by 3 clock for a 1.5 c performance improvement faster instructions, especially indexed/indirect data operations 1.725 m s 16 x 16 multiply with 16 mhz clock (is 6.25 m s on the 8096) faster interrupt response (almost twice as fast) powerdown and idle modes 6 new instructions 8 new interrupt vectors/6 new interrupt sources peripheral features sfr window switching allows read-only sfrs to be written and vice-versa timer 2 can count up and down by external selec- tion timer 2 has an independent capture register on ris- ing edges of (p2.7) hso line events are stored in a register hso has cam lock and cam clear commands new baud rate values are needed for serial port, which enables higher speeds in all modes. double buffered serial port transmit register (before, only receive was double buffered) serial port receive overrun and framing error detec- tion pwm has a divide by 2 prescaler hold/hlda bus protocol thermal characteristics plcc i ja 35 c/w i jc 12 c/w max case 135 c temperature new instructions pusha pushes the psw, imask, imask1 and wsr (used instead of pushf when us- ing the new interrupts and registers) popa pops the psw, imask, imask1 and wsr (used instead of popf when using the new interrupts and registers) 2
automotive 8XC196KB idlpd sets the device into idle or powerdown mode. the instruction has the following format: idlpd y key (where key e 1 for idle and key e 2 for powerdown. illegal keys are processed, but no action is tak- en. cmpl compare 2 long direct values. only the direct addressing mode is supported for this instruction and the format follows the cmp format. bmov block move using 2 auto-incrementing pointers and a counter. the instruction has the following format: bmov iptr.wcnt. the iptr is a long word, with the low word being the address of the source and the upper word being the address of the destination. wcnt is the number of words to be transferred. djnzw * decrement jump not zero using a word counter. the instruction format follows the djnz instruction. * see the functional deviations section for details. sfr operation all of the registers that were present on the 8096 work the same way as they did, except that the baud rate value will be different on the 8XC196KB. the new registers shown in the memory map control new functions. the most important register is the window select register (wsr) which allows the reading of the formerly write-only registers, and vice-versa. packaging the 8XC196KB is available in 68-pin plastic leaded chip carrier (plcc) and 68-pin cerquad pack- ages. contact your local sales office to determine the exact ordering code for the part desired. 270679 2 figure 3. 68-pin plcc package 3
automotive 8XC196KB plcc description 9 ach7/po.7/pmd3 8 ach6/po.6/pmd2 7 ach2/po.2 6 ach0/po.0 5 ach1/po.1 4 ach3/po.3 3 nmi 2ea 1v cc 68 v ss 67 xtal1 66 xtal2 65 clkout 64 buswidth 63 inst 62 ale/adv 61 rd 60 ad0/p3.0 59 ad1/p3.1 58 ad2/p3.2 57 ad3/p3.3 56 ad4/p3.4 55 ad5/p3.5 54 ad6/p3.6 53 ad7/p3.7 52 ad8/p4.0 51 ad9/p4.1 50 ad10/p4.2 49 ad11/p4.3 48 ad12/p4.4 47 ad13/p4.5 46 ad14/p4.6 45 ad15/p4.7 44 t2clk/p2.3 plcc description 43 ready 42 t2rst/p2.4/ainc 41 bhe /wrh 40 wr /wrl 39 pwm/p2.5 38 p2.7/t2capture/pact 37 v pp 36 v ss 35 hso.3 34 hso.2 33 p2.6 32 p1.7/hold 31 p1.6/hlda 30 p1.5/breq 29 hso.1 28 hso.0 27 hso.5/hsi.3/sid3 26 hso.4/hsi.2/sid2 25 hsi.1/sid1 24 hsi.0/sid0 23 p1.4 22 p1.3 21 p1.2 20 p1.1 19 p1.0 18 txd/p2.0/pver 17 rxd/p2.1/pale 16 reset 15 extint/p2.2/prog 14 v ss 13 v ref 12 angnd 11 ach4/p0.4/pmd0 10 ach4/p0.5/pmd1 figure 4. plcc functional pinouts 4
automotive 8XC196KB pin descriptions symbol name and function v cc main supply voltage ( a 5v) v ss digital circuit ground (0v). there are three v ss pins, all of which must be connected. v ref reference for the a/d converter ( a 5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . v pp programming voltage for the eprom parts. it should be a 12.75v for programming. this pin was v bb on 8x9x-90 parts. it is also the timing pin for the return from powerdown circuit. connect this pin with a 1 m f capacitor to v ss anda1m x resistor to v cc . if this function is not used, v pp may be tied to v cc . xtal1 input of the oscillator inverter and the internal clock generator xtal2 output of the oscillator inverter clkout output of the internal clock generator. the frequency of clkout is (/2 the oscillator frequency. it has a 50% duty cycle. reset reset input to the chip. input low for at least 4 state times will reset the chip. the subsequent low to high transition resynchronizes clkout and commences a 10-state time sequence in which the psw is cleared, a byte is read from 2018h loading the ccb, and a jump to location 2080h is executed. input high for normal operation. reset has an internal pullup. buswidth input for bus width selection. if ccr bit 1 is a one, this pin selects the buswidth for the bus cycle in progress. if buswidth is low, an 8-bit cycle occurs. if buswidth is high, a 16-bit cycle occurs. if ccr bit 1 is a 0, the bus is always an 8-bit bus. this pin is the test pin on the 8x9x-90 parts. systems with test tied to v cc need not change. nmi a positive transition causes an interrupt vector through external memory location 203eh. inst output high during an external memory read. indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is active only during external memory fetches, during internal eprom/rom fetches inst is held low. ea input for memory select (external access). ea equal to a ttl-high causes memory accesses to locations 2000h through 3fffh to be directed to on-chip eprom/rom. ea equal to a ttl-low causes accesses to these locations to be directed to off-chip memory. ea e a 12.75v causes execution to begin in the programming mode. ea has an internal pulldown, so it defaults to execute from external memory, unless otherwise driven. ea is latched at reset. ale/adv address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when the pin is adv , it goes inactive (high) at the end of the bus cycle. adv can be used as a chip select for external memory. ale/adv is active only during external memory accesses. 5
automotive 8XC196KB pin descriptions (continued) symbol name and function rd read signal output to external memory. rd is active only during external memory reads. wr /wrl write and write low output to external memory, as selected by the ccr. wr will go low for every external write, while wrl will go low only for external writes where an even byte is being written. wr /wrl is active during external memory writes. bhe /wrh byte high enable or write high output as selected by the ccr. bhe e 0 selects the bank of memory that is connected to the high byte of the data bus. a0 e 0 selects that bank of memory that is connected to the low byte. thus accesses to a 16-bit wide memory can be to the low byte only (a0 e 0, bhe e 1), to the high byte only (a0 e 1, bhe e 0) or both bytes (a0 e 0, bhe e 0). if the wrh function is selected, the pin will go low if the bus cycle is writing to an odd memory location. bhe /wrh is only valid during 16-bit external memory write cycles. ready ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. if the pin is high, cpu operation continues in a normal manner. if the pin is low prior to the falling edge of clkout, the memory controller goes into a wait state mode until the next positive transition in clkout occurs with ready high. when external memory is not used, ready has no effect. the number of wait states inserted into the bus cycle is controlled by the ccr. hsi inputs to high speed input unit. four hsi pins are available: hsi.0, hsi.1, hsi.2, hsi.3. two of which are shared with the hso unit (hsi.2 and hsi.3). the hsi pins are also used as the sid in slave programming mode. hso outputs from high speed output unit. six hso pins are available (hso.0 through hso.5). hso.4 and hso.5 are shared with hsi. port 0 8-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. these pins are also used as inputs to eprom parts to select the programming mode. port 1 8-bit quasi-bidirectional i/o port. port 2 8-bit multi-functional port. all of its pins are shared with other functions. port 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. hold bus hold input requesting control of the bus. enabled by setting wsr.7 hlda bus hold acknowledge output indicating release of the bus. enabled by setting wsr.7. breq bus request output. activated when the bus controller has a pending external memory cycle. enabled by setting wsr.7. 6
automotive 8XC196KB electrical characteristics absolute maximum ratings * storage temperature b 60 cto a 150 c voltage from v pp or ea to v ss or angnd b 0.5v to a 13.0v voltage on any pin to v ss or angnd b 0.5v to a 7.0v this includes v pp on rom and cpu devices. power dissipation1.5w notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol parameter min max units t a ambient temperature under bias b 40 a 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v f osc oscillator frequency 3.5 16 mhz note: angnd and v ss should be nominally at the same potential. dc characteristics (under listed operating conditions) symbol parameter min typ max units test conditions i cc v cc supply current 50 70 ma xtal1 e 16 mhz, ( b 40 cto a 125 c ambient) v cc e v pp e v ref e 5.5v i pd powerdown mode current 5 m av cc e v pp e v ref e 5.5v i ref a/d reference 2 5 ma xtal1 e 16 mhz, supply current v cc e v pp e v ref e 5.5v i idle idle mode current 10 35 ma xtal1 e 16 mhz, v cc e v pp e v ref e 5.5v v il input low voltage b 0.5v a 0.8 v v ih input high voltage (1) 0.2 v cc a 1.1 v cc a 0.5 v v ih1 input high voltage on xtal1 0.7 v cc v cc a 0.5 v v ih2 input on high voltage 2.6 v cc a 0.5 v on reset v ol output low voltage 0.3 v i ol e 200 m a 0.45 v i ol e 3.2 ma 1.5 v i ol e 7.0 ma v oh output high voltage v cc b 0.3 v i oh eb 200 m a (standard outputs) v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7.0 ma v oh1 output high voltage v cc b 0.3 v i oh eb 15 m a (quasi-bidirectional v cc b 0.7 v i oh eb 30 m a outputs) v cc b 1.5 v i oh eb 60 m a 7
automotive 8XC196KB dc characteristics (under listed operating conditions) (continued) symbol parameter min typ max units test conditions i li input leakage current g 10 m a0 k v in k v cc b 0.3v (std. inputs) i li1 input leakage current g 3 m a0 k v in k v ref (port 0) i tl 1 to 0 transition current b 800 m av in e 2.0v (qbd pins) i il logical 0 input current b 50 m av in e 0.45v (qbd pins) i il1 logical 0 input current b 9mav in e 0.45v in reset (ale, rd , inst) i il2 logical 0 input current in b 700 m av in e 0.45v reset (wr, p2.0, bhe) hyst hysteresis on reset pin 250 mv r rst reset pullup resistor 6k 50 x c s pin capacitance 10 pf f test e 1.0 mhz (any pin to v ss ) notes: (notes apply to all specifications) 1. all pins except reset and xtal1. qbc (quasi-bidirectional) pins include port 1, p2.6, p2.7. 2. standard outputs include ad0 15, rd ,wr , ale, bhe , inst, hso pins, pwm/p2.5, clkout, reset, port 3 and 4, txd/p2.0 and rxd (in serial mode 0). the v oh specification is not valid for reset. ports 3 and 4 are open drain outputs. 3. standard inputs include hsi pins, cde, ea , ready, buswidth, nmi, rxd/p2.1, extint/p2.2, t2clk/p2.3 and t2rst/p2.4 4. maximum current per pin must be externally limited to the following values if v ol is held above 0.45v or v oh is held below v cc b 0.7v: i ol on output pins: 10 ma i ol on qbd pins: self limiting i ol on standard output pins: 10 ma 5. maximum current per bus pin (data and control) during normal operation is g 3.2 ma. 6. during normal (non-transient) conditions the following total current limits apply: port 1, p2.6 i ol :29ma i oh : is self limiting hso, p2.0, rxd, reset i ol :29ma i oh :26ma p2.5, p2.7, wr , bhe i ol :13ma i oh :11ma ad0 ad15 i ol :52ma i oh :52ma rd , ale, inst, clkout i ol :13ma i oh :13ma 7. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref e v cc e 5v. i cc max e 3.88 c freq a 8.43 i idle max e 1.65 c freq a 5.2 270679 9 i cc typ e 2.5 c freq a 8.0 i idle typ e 0.5 c freq a 3.2 figure 5. i cc vs frequency 8
automotive 8XC196KB ac characteristics over specified operating conditions test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz the system must meet these specifications to work with the 8XC196KB symbol parameter min max units t avyv address valid to ready setup 2 t osc b 75 ns t llyv ale low to ready setup t osc b 60 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (1) t llyx ready hold after ale low t osc b 15 2 t osc b 40 ns (1) t avgv address valid to buswidth setup 2 t osc b 75 ns t llgv ale low to buswidth setup t osc b 60 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns t rldv rd active to input data valid t osc b 23 ns t cldv clkout low to input data valid t osc b 50 ns t rhdz end of rd to input data float t osc b 20 ns t rxdx data hold after rd inactive 0 ns f xtal oscillator frequency 3.5 16 mhz t osc oscillator period (1/f xtal ) 62.5 286 ns t xhch xtal1 high to clkout high or low (1) 20 110 ns t clcl clkout period 2 t osc ns t chcl clkout high period t osc b 10 t osc a 10 ns t cllh clkout falling edge to ale rising b 10 10 ns t llch ale/adv falling edge to clkout rising b 15 15 ns t lhlh ale/adv cycle time 4 t osc ns t lhll ale/adv high period t osc b 10 t osc a 10 ns t avll address setup to ale/adv falling edge t osc b 30 ns t llax address hold after ale/adv falling edge t osc b 40 ns t llrl ale/adv falling edge to rd falling edge t osc b 35 ns t rlcl rd low to clkout falling edge 4 25 ns t rlrh rd low period t osc b 10 t osc a 25 ns t rhlh rd rising edge to ale/adv t osc t osc a 25 ns rising edge (3) t rlaz rd low to address float 5 ns t llwl ale/adv falling edge to wr falling edge t osc b 10 ns t clwl clkout low to wr falling edge 0 25 ns t qvwh data stable to wr rising edge t osc b 23 ns t chwh clkout high to wr rising edge b 515ns t wlwh wr low period t osc b 15 t osc a 5ns 9
automotive 8XC196KB ac characteristics over specified operating conditions (continued) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz the system must meet these specifications to work with the 8XC196KB symbol parameter min max units t whqx data hold after wr rising edge t osc b 15 ns t whlh wr rising edge to ale/adv t osc b 20 t osc a 10 ns rising edge (3) t whbx bhe , inst, hold after wr ,rd rising edge t osc b 15 ns t whax ad8 15 hold after wr /rd t osc b 30 ns rising edge t rhbx bhe , inst hold after rd rising t osc b 10 ns t rhax ad8 15 hold after rd rising t osc b 25 ns notes: 1. typical specification, not guaranteed. 2. assuming back-to-back bus cycles. t osc e 62.5 ns at 16 mhz; t osc e 100 ns at 10 mhz; t osc e 125 ns at 8 mhz. system bus timing 270679 4 10
automotive 8XC196KB ready/buswidth timing 270679 5 hold /hlda timings symbol description min max units notes t hvch hold setup 1 80c196kb 75 ns 83c196kb 85 t clhal clkout low to hlda low b 15 15 ns t clbrl clkout low to breq low b 15 15 ns t halaz hlda low to address float 80c196kb 15 ns 83c196kb 20 t halbz hlda low to bhe, inst, rd, wr float ns t clhah clkout low to hlda high b 15 15 ns t clbrh clkout low to breq high b 15 15 ns t hahax hlda high to address no longer float b 5ns t hahbv hlda high to bhe , inst, rd ,wr valid b 20 ns t cllh clkout low to ale high b 515 ns note: 1. to guarantee recognition at next clock. 11
automotive 8XC196KB 270679 27 external clock drive symbol parameter min max units 1/t xlxl oscillator frequency 3.5 16 mhz t xlxl oscillator period (t osc ) 62.5 286 ns t xhxx high time t osc b 51 ns t xlxx low time t osc b 51 ns t xlxh rise time t osc b 73 ns t xhxl fall time t osc b 73 ns external clock drive waveforms 270679 6 12
automotive 8XC196KB ac testing input, output waveforms 270679 7 ac testing inputs are driven at 2.4v for logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at 2.0v for a logic ``1'' and 0.8v for logic ``0''. float waveforms 270679 8 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs i ol /i oh s g 15 ma. explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: signals: he high ae address le ale/adv le low be bhe re rd ve valid ce clkout we wr /wrh /wri xe no longer valid de data xe xtal1 ze floating gebuswidth ye ready ac characteristicseserial porteshift register mode serial port timingeshift register mode test conditions: t c eb 40 cto a 125 c; v cc e 5.0v g 10%; v ss e 0.0v; load capacitance e 80 pf symbol parameter min max unit t xlxl serial port clock period (9) 6t osc /4 t osc ns t xlxh serial port clock falling edge 4 t osc b 50/2 t osc b 50 4 t osc a 50/2 t osc b 50 ns to rising edge (9) t qvxh output data setup to clock rising edge 2 t osc b 50 ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid 2 t osc a 50 ns after clock rising edge t dvxh input data setup to clock rising edge t osc a 50 ns t xhdx (8) input data hold after clock rising edge 0 ns t xhqz (8) last clock rising to output float t osc ns notes: 8. parameter not tested. 9. baud rate register t 8002h/baud rate register e 8001h. 13
automotive 8XC196KB a to d characteristics there are two modes of a/d operation: with and without clock prescaler. the modes are shown in the table below. in mode 2, with the clock prescaler dis- abled, the maximum xtal1 frequency is 8.0 mhz. accuracy will degrade at higher frequencies in this mode. the frequency divider option is provided to obtain higher accuracy outside of the currently spec- ified operating conditions. the converter is ratiometric, so the absolute accura- cy is directly dependent on the accuracy and stability of v ref .v ref must be close to v cc since it supplies both the resister ladder and the digital section of the converter. a/d converter specifications the specifications given below assume adherence to the operating conditions section of this data sheet. testing is performed in mode 2 with v ref e 5.12v and 8 mhz operating clock frequency. waveformeserial porteshift register mode serial port waveformeshift register mode 270679 28 clock prescaler on clock prescaler off ioc2.4 e 0 ioc2.4 e 1 mode 1e 158 states for execution mode 2e 91 states for execution 26.33 m s @ 12 mhz 22.75 m s @ 8 mhz (maximum) note: ioc2.3 e 0, the no sample and hold feature is not available on the 8XC196KB device. 14
automotive 8XC196KB parameter typical * (1) minimum maximum units ** resolution 512 1024 level 9 10 bits absolute error 0 g 6 lsbs full scale error 0.25 g 0.5 lsbs zero offset error b 0.25 g 0.5 lsbs non-linearity 1.5 g 2.5 0 g 4 lsbs differential non-linearity l b 1 a 2 lsbs channel-to-channel matching g 0.1 0 g 1 lsbs repeatability g 0.25 lsbs (1) temperature coefficients: offset 0.009 lsb/c (1) full scale 0.009 lsb/c (1) differential non-linearity 0.009 lsb/c (1) off isolation b 60 db (1, 2, 4) feedthrough b 60 db (1, 2) v cc power supply rejection b 60 db (1, 2) input resistance 1k 5k x (1) dc input leakage 0 3 m a sample time (prescaler on/off) 15/8 states (3) input capacitance 3 pf notes: * these values are expected for most parts at 25 c but are not tested or guaranteed. ** an ``lsb'', as used here, has a value of approximately 5 mv. (see automotive handbook, for a/d glossary of terms. 1. these values are not tested in production and are based on theoretical estimates and/or laboratory test. 2. dc to 100 khz. 3. one state e 125 ns @ 16 mhz; 333 ns @ 6 mhz. 4. multiplexer break-before-make guaranteed. 80c196kb functional deviations the 80c196kb has the following problems. 1. the hsi unit has two errata: one dealing with res- olution and the other with first entries into the fifo. the hsi resolution is 9 states instead of 8 states. events on the same line may be lost if they occur faster than once every 9 state times. there is a mismatch between the 9 state time hsi resolution and the 8 state time timer. this causes one time value to be unused every 9 timer counts. events may receive a time-tag one count later than expected because of this ``skipped'' time val- ue. if the first two events into an empty fifo (not including the holding register) occur in the same internal phase, both are recorded with one time- tag. otherwise, if the second event occurs within 9 states after the first, its time-tag is one count later than the first's. if this is the ``skipped'' time value, the second event's time-tag is 2 counts lat- er than the first's. if the fifo and holding register are empty, the first event will transfer into the holding register after 8 state times, leaving the fifo empty again. if the second event occurs after this time, it will act as a new first event into an empty fifo. 2. if an a/d conversion in progress is aborted by starting a new a/d conversion, results of the sec- ond conversion may be inaccurate. 15
automotive 8XC196KB the work-around is to wait for the conversion in progress to finish before starting the second con- version. polling or an interrupt will detect the con- version completion. 3. if the unsigned divide instruction (word or byte) is in the queue as hold or ready is asserted, the result may be incorrect. techbit (mc1791). (b-step only.) differences between the 80c196ka and the 80c196kb the 8XC196KB is identical to 8xc196ka except for the following differences. 1. ale is high after reset on the 80c196kb instead of low as on the 80c196ka. 2. the djnzw instruction is not guaranteed to work on the 80c196kb. (a-step only.) 3. the hold /hlda bus protocol is available on the 80c196kb. converting from other 8096bh family products to the 80c196kb the following list of suggestions for designing an 809xbh system will yield a design that is easily con- verted to the 80c196kb. 1. do not base critical timing loops on instruction or peripheral execution times. 2. use equate statements to set all timing parame- ters, including the baud rate. 3. do not base hardware timings on clkout or xtal1. the timings of the 80c196kb are differ- ent than those of the 8x9xbh, but they will func- tion with standard rom/eprom/peripheral type memory systems. 4. make sure all inputs are tied high or low and not left floating. 5. indexed and indirect operations relative to the stack pointer (sp) work differently on the 80c196kb than on the 8096bh. on the 8096bh, the address is calculated based on the un-updat- ed version of the stack pointer. the 80c196kb uses the updated version. the offset for pop [ sp ] and pop nn [ sp ] instructions may need to be changed by a count of 2. 6. the v pd pin on the 8096bh has changed to a v ss pin on the 80c196kb. other design considerations (kb b-0 to kb c-1) 1. the nmi pin on the kb rom (c-1) has a weak pulldown. i ih1 max is 100 m a. the kb rom (b-0) did not have a pulldown on nmi. if kb rom (b-0) designs have nmi tied to v cc , the nmi pin must be tied to v ss . if nmi is tied to v ss or is floating, it is okay. 2. the ale, rd, and inst pins on the kb rom (c-1) have stronger pullups during reset than on the kb rom (b-0). i il1 is b 7maonthekb rom (c-1) compared to b 1.2 ma on the kb rom (b-0). designs which pull these pins low to enter once mode must have strong enough pull- downs to overcome the pullups. 3. pin on the plcc package on the kb rom (b-0) was the cde pin. that function did not work so the pin was assigned to v ss . on the kb rom (c-1) this pin is tied directly to v ss on the device and must be tied to v ss externally. 4. several ac/dc specifications have changed. (see data sheet revision history; review them carefully.) 16
automotive 8XC196KB data sheet revision history this is the -005 revision of the 8XC196KB data sheet and is valid for devices marked with a ``f'' or ``g'' at the end of the topside tracking number. the following differences exist between the -004 revision and the -005 revision: 1. all performance related data is now quoted at 16 mhz. the maximum clock rate has changed from 12 mhz to 16 mhz. 2. max power dissipation changes from 0.43w to 1.5w. 3. i cc max has changed from 60 ma to 70 ma. 4. i cc typical has changed from 40 ma to 50 ma. 5. i ref typical has changed from 1 ma to 2 ma. 6. i idle has changed from 25 ma to 35 ma. 7. v ih2 min has changed from 2.4v to 2.5v. 8. v oh1 test condition for v cc b 0.3v has changed from b 7 m ato b 15 m a. 9. i tl has changed from b 650 m ato b 800 m a. 10. i il1 has changed from b 1.2 ma to b 9 ma. 11. i il1 now only applies to ale, rd and inst. 12. r rst max has changed from 100 k x to 50 k x . 13. added spec for reset pin hysteresis and i il2 for wr, p2.0, and bhe. 14. t avyv has changed from 2 t osc b 85 ns to 2t osc b 75 ns. 15. t llyv has changed from t osc b 72 ns to t osc b 60 ns. 16. t avgv has changed from 2 t osc b 85 ns to 2t osc b 75 ns. 17. t avdv has changed from 3 t osc b 65 ns to 3t osc b 55 ns. 18. f xtal max has changed from 12 mhz to 16 mhz. 19. t osc min has changed from 83 ns to 62.5 ns. 20. t xhch min has changed from 40 ns to 20 ns. 21. t cllh min/max has changed from b 5 ns/15 ns to b 10 ns/10 ns. 22. t lhll min/max has changed from t osc g 12 ns to t osc g 10 ns. 23. t avll has changed from t osc b 20 ns to t osc b 30 ns. 24. t llrl has changed from t osc b 40 ns to t osc b 35 ns. 25. t rlcl min/max has changed from 5 ns/30 ns to 4 ns/25 ns. 26. t rlrh has changed from t osc b 5nstot osc b 10 ns. 27. t rlaz has changed from 12 ns to 5 ns. 28. t chwh min/max has changed from b 10 ns/ 10 ns to b 5 ns/15 ns. 29. t wlwh min/max has changed from t osc b 30 ns to t osc b 15 ns. 30. t whqx has changed from t osc b 10 ns to t osc b 15 ns. 31. t whlh min/max has changed from t osc b 10 ns/t osc a 15 ns to t osc b 20 ns/t osc a 10 ns. 32. t whbx has changed from t osc b 10 ns to t osc b 15 ns. 33. t whax has changed from t osc b 50 ns to t osc b 30 ns. 34. t rhax has changed from t osc b 50 ns to t osc b 25 ns. 35. functional deviation number 1 has been re- moved (djwz is now functional). 36. functional deviation number 3 has been re- moved (sio framing flag now works correctly). 37. functional deviation number 5 has been re- moved (sio ri now correctly generated). 38. functional deviation number 6 has been cor- rected. the divide during hold bug has been fixed. 39. the section ``other design considerations kb b-0 to kb c-1'' has been added. 17

▲Up To Search▲

Price & Availability of 8XC196KB

	To Download 8XC196KB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .